The AI Boom Has a Glue Problem
TSMC can fabricate more raw GPU dies than the world currently needs. The actual chokepoint sits one step later — stitching each chip to its memory — and Nvidia has already reserved more than half the world's capacity to do it.
Why the shortage doesn't close even as capacity doubles
Indexed model, not real wafer counts: both lines are normalized so industry CoWoS demand reaches 100 in December 2026. Capacity is modeled shrinking the reported shortfall linearly from ~20% in January to ~10% in December, matching TrendForce's reported gap-narrowing trend for 2026 — the real month-to-month path is uneven. Drag the slider or press Run to move through the year and watch the gap persist even as both lines climb.
The plain version
Here's a strange fact about the AI chip shortage: the chip itself usually isn't the scarce part. TSMC, the company that actually manufactures the silicon inside an Nvidia GPU, can already produce more raw chips than the world currently needs. The real wait happens one step later, during a process almost nobody outside the industry has heard of, called CoWoS.
Think of it like this: making the chip is like baking thousands of identical cakes — TSMC's factories are extremely good at that part, and fast. But a finished AI chip on its own is useless. It has to sit right next to a stack of ultra-fast memory chips so the two can trade data billions of times a second, and wiring that connection together is delicate, precision work — closer to a jeweler setting a watch than a factory stamping parts. Only a handful of facilities on Earth know how to do it at the scale the AI boom needs. That gluing-and-wiring step is CoWoS, and it's where the entire industry gets stuck in line.
The scale of the squeeze: the whole industry wants roughly a million of these packaging "seats" in 2026 — nearly three times what it wanted just two years ago. TSMC is racing to add capacity, doubling its output over the year, but even by December it's expected to still fall short by around 10%. And Nvidia alone has already reserved more than half of everything TSMC can produce, leaving AMD, Google, Amazon, and every startup building its own AI chip to fight over what's left.
So next time you hear "chip shortage," picture less a shortage of silicon and more a shortage of the world's most precise glue gun.
The expert version
CoWoS — Chip-on-Wafer-on-Substrate — is TSMC's 2.5D advanced-packaging platform, and in 2026 it is the binding constraint on AI accelerator supply, not front-end logic fabrication. The problem is physical: an HBM stack needs thousands of I/O connections crammed into a footprint far too small for standard PCB or even organic-substrate trace pitches (roughly 100+ microns) to route. CoWoS solves this by placing the GPU logic die and multiple HBM stacks side-by-side on a passive silicon interposer carrying tens of thousands of micron-scale routing traces and through-silicon vias (TSVs) — effectively an ultra-dense circuit board etched directly into silicon. That interposer-plus-dies assembly is then mounted onto an organic substrate and soldered to the board. It remains the only economical way to deliver the multi-terabyte-per-second bandwidth HBM3E and HBM4 require.
The bottleneck is capacity, not know-how. TrendForce estimates total CoWoS demand rose from roughly 370,000 wafers in 2024 to about 670,000 in 2025 and will approach 1 million in 2026 — nearly tripling in two years, driven almost entirely by AI accelerators. TSMC's own monthly capacity is projected to reach 120,000–140,000 wafers by end-2026, roughly double where it started the year, with outsourced assembly and test (OSAT) partners such as Amkor and ASE now taking on front-end CoWoS steps TSMC has begun subcontracting to add another 50,000–60,000 wafers a month. Even combined, TrendForce projects the supply-demand gap only narrows from about 20% to roughly 10% by December 2026 — it does not close.
Allocation compounds the squeeze. Nvidia has reportedly locked in 800,000–850,000 CoWoS wafers for 2026, over half of TSMC's total, leaving AMD, hyperscalers' in-house silicon (Google TPU, Amazon Trainium, Microsoft Maia), and merchant AI-chip startups to compete for what remains. TSMC has responded by lifting its 2027 capex guidance to roughly $85 billion, with a large share aimed at packaging and interposer capacity — but hybrid-bonding and thermal-compression-bonding tool sets take years to qualify at volume, so the structural constraint persists well past this capex cycle.
Why it matters for tech + supply chain: the gating factor on who ships AI servers in 2026-27 isn't how many chips a company can order — it's how much packaging capacity it locked down months ago, which is why Nvidia's early reservations are as strategically important as its chip designs.
Why it matters for tech + supply chain: it reframes AI capex risk — wafer starts are a multi-fab, multi-node problem with real substitution options, but CoWoS allocation is a single-vendor-plus-a-few-OSATs problem with a multi-year tooling ramp, which is pulling serious capital and M&A interest into advanced-packaging and OSAT players (Amkor, ASE) that used to be an afterthought in the AI supply chain.