AI Chip Packages Are Starting to Warp Like Potato Chips. The Billion-Dollar Fix Keeps Missing Its Ship Date.
Today's biggest AI accelerators cram a giant compute die next to towers of memory onto a single plastic-cored package — and that package is now large enough to bow during manufacturing, risking cracked solder joints. The industry's fix is a substrate made of glass. It's been "almost ready" since 2024.
Same package, two substrate materials: watch the bow
Illustrative model, not a precision engineering simulation — bow ≈ k × |CTE(substrate) − CTE(silicon)| × ΔT × size², with k calibrated so the organic curve crosses a rough "crack-risk" line (~150µm) right around the 80-120mm package sizes today's largest AI accelerators actually use. Drag the slider or hit Grow to change package size and watch each material respond against the same red risk line.
For reference: mainstream laptop/phone chip packages run roughly 20-40mm per side; today's largest AI accelerator packages (compute die + several HBM stacks) run roughly 80-120mm per side.
The plain version
Think about a bimetallic strip in an old thermostat: two metals bonded together that expand at different rates, so when the temperature changes, the strip curls. Advanced chip packages have the same problem. Manufacturing glues a silicon chip onto a plastic-and-resin base at temperatures above 200°C. As it cools back to room temperature, the plastic shrinks about six times more than the silicon sitting on top of it. On a small chip, that mismatch is invisible. But today's AI accelerators are enormous by chip standards — one giant compute chip sitting beside 8 to 12 towers of memory, all packed onto a single base that can be as wide as a coaster. At that size, the shrinking mismatch is big enough to visibly bow the whole package, like a potato chip warping on a hot windshield. Bow it enough, and the microscopic solder balls connecting the chip to the circuit board start to crack — turning a chip that can cost more than a car into scrap.
The fix everyone in the industry agrees on: stop using plastic. Swap in a thin sheet of specialized glass, which expands and contracts at almost the same rate as silicon, so the package barely bends no matter how big it gets. The catch is that glass is also brittle — good at not stretching, bad at not shattering — so drilling thousands of hair-thin connective holes through it without cracking it has turned out to be its own multi-year engineering slog.
A company called Absolics has run a dedicated glass-substrate factory in Georgia, backed partly by U.S. government CHIPS Act money, since 2022 — and has been "about to" reach mass production ever since, missing the date it originally set for 2024 more than once. Intel, Samsung and Taiwan's TSMC are all racing versions of the same fix, aiming for real volume production sometime around 2027 to 2028.
The twist: nobody talks about AI chip progress in terms of glue and plastic. But right now, the size and memory capacity of the world's most advanced AI chips is limited less by how small a transistor can get, and more by how big a piece of plastic can bend before it cracks.
The expert version
The constraint is coefficient-of-thermal-expansion (CTE) mismatch inside the package, not the reticle limit itself — though the two are related. A single lithography exposure is capped at roughly 26mm × 33mm (about 858mm²), which is why large AI accelerators are built from multiple chiplets and HBM stacks tiled across an interposer and mounted on a package substrate rather than fabricated as one monolithic die. That substrate — typically an ABF (Ajinomoto build-up film) or BT-resin laminate core — has a CTE around 17 ppm/°C, versus roughly 2.6 ppm/°C for monocrystalline silicon. During die-attach and underfill cure (reflow well above 200°C, followed by cooldown to ambient), the differential contraction generates a bending moment across the stack-up, analogous to a bimetallic strip, producing package bow scaling roughly with CTE mismatch, ΔT, and the square of lateral package size, inversely with substrate thickness. At the 100-120mm footprints now common for reticle-stitched GPU/accelerator packages carrying 8-12 HBM stacks beside a large compute die, bow can reach several hundred microns — enough to exceed the fatigue/elastic limits of C4 and microbump solder joints, with failure concentrated at die corners where stress is highest.
Glass cores (aluminosilicate or borosilicate formulations) bring CTE to roughly 3.5-4 ppm/°C — near-matched to silicon — plus superior flatness and lower dielectric loss than organic laminates, enabling both larger reticle-stitched panels and denser, lower-loss signal routing. The trade-off is mechanical: glass has essentially no plastic deformation regime, so stress that an organic laminate would absorb by yielding instead propagates as a crack, making through-glass-via (TGV) drilling and panel handling failure modes that took years to de-risk. On manufacturing status: Absolics (an SKC affiliate) operates a 120,000 sq ft Covington, Georgia facility, backed by up to $75 million in preliminary CHIPS Act funding, and has been supplying qualification-stage samples to AMD and AWS while scaling capacity from roughly 5,000 toward a targeted 20,000 panels per month — with its own mass-production date having slipped from an original H1 2024 target to repeated "by year-end" restatements. Intel, which has committed over $1 billion to glass substrates since 2023, demonstrated an EMIB-plus-glass-core assembly with zero observed microcracking ("No SeWaRe") in January 2026, still short of a shipping product. Samsung Electro-Mechanics and Sumitomo Chemical's Dongwoo Fine-Chem formed a glass-core joint venture targeting second-half-2027 production; TSMC's CoPoS line targets 2027 pilot and second-half-2028 mass production. Industry trade coverage is consistent on one point: despite years of "imminent" announcements, real volume production remains 2027-2030 out.
Why it matters for tech + supply chain: the ceiling on how big and how memory-dense the world's most advanced AI chips can get isn't set by clever engineering anymore — it's set by whether a handful of factories can mass-produce a sheet of brittle glass without cracking it.
Why it matters for tech + supply chain: advanced packaging, not lithography, is now the gating factor on how much compute and HBM an AI accelerator vendor can integrate per package — and that gate is held by a handful of substrate suppliers still stuck in qualification, years behind their own announced timelines.