Samsung's HBM4 Yield Went From Under 60% to 80% in Six Months. On a 12-Layer Memory Stack, That's the Difference Between Profit and Scrap.
The memory that feeds Nvidia's newest AI chips isn't one chip — it's a tower of a dozen wired together, and a single bad layer can wreck the whole thing. That's why a Korean factory's yield number just became one of the most closely watched figures in the entire AI supply chain.
One bad layer scraps the whole stack
Set a per-die pass rate, pick a stack height, then press Run to build a stack layer by layer and see if it survives. Simplified model: treats every memory die's pass/fail as independent and ignores real fabs' known-good-die testing and redundant wiring, which claw back some yield in practice — the compounding math is still the real reason more layers make yield dramatically harder.
Press Run to build a 12-hi stack at 97.0% per-die pass rate.
The plain version
Every high-end AI chip today needs a special kind of memory called HBM — not one chip, but a tower of up to a dozen tiny memory chips glued directly on top of each other and wired straight down through microscopic tunnels drilled through the silicon. Building that tower is one of the hardest tricks in electronics, because of a brutal rule: if even one layer in the stack has a flaw, the whole tower usually gets thrown away. It doesn't matter if the other eleven layers were perfect.
That's why "yield" — the share of finished stacks that actually work — is one of the most closely watched numbers in the entire AI chip supply chain right now. In February, Samsung's HBM4 stacks were passing well under 60% of the time. By August, that number hit roughly 80%, a level the industry calls "golden yield" — good enough to sell in real volume instead of handing out samples. Six months, about twenty extra points, and it's the difference between Samsung becoming a real second supplier for Nvidia's newest AI GPUs, or staying stuck behind SK Hynix, which currently ships most of that memory.
Here's the twist: to get there, both companies redesigned the bottom layer of the stack — the "base die," which handles traffic control instead of storing data — and each is now leaning on outside manufacturing to build it, using more advanced chipmaking than memory companies usually touch. Even the two biggest memory makers on Earth can't do this entirely alone anymore.
Which is exactly why one Korean factory's yield number moving from 60% to 80% ripples all the way out to how many AI chips the whole industry can actually ship next year — memory, not the GPU itself, is turning into the thing that decides the pace.
The expert version
HBM4 — the memory standard behind Nvidia's Vera Rubin GPU platform and AMD's next Instinct accelerators — hits its bandwidth and capacity targets by stacking DRAM dies vertically and linking them with through-silicon vias (TSVs): copper-filled vertical channels etched straight through each die, bonded to the dies above and below through microbumps at a tighter pitch than HBM3E used. In JEDEC's naming, "12-hi" and "16-hi" refer specifically to the number of stacked DRAM core dies, sitting atop one separately built base die that handles I/O and memory-controller logic. Mainstream HBM3E ships mostly at 8-hi; HBM4 standardizes on 12-hi, with 16-hi variants planned for HBM4E.
The yield mechanics are unforgiving because, to a first approximation and ignoring built-in TSV redundancy and known-good-die screening, overall stack yield ≈ (per-die yield)^n. A 12-hi stack at a hypothetical 97% per-die yield lands near 69%; nudging per-die yield to roughly 98% pushes it close to 79-80% — illustrating, at the order-of-magnitude level, why moving from sub-60% to an 80% "golden yield" between February and August 2026 registered industry-wide as a landmark rather than an incremental step.
The structural shift in HBM4 is where the base die gets fabricated. Earlier HBM generations built the base die on the same DRAM process as the stack above it; HBM4 instead moves it to a separate, more advanced logic node, because logic transistors scale and switch far more efficiently there than on a DRAM process. SK Hynix has reportedly adopted TSMC's N12 (12nm-class) node for its base die, said to drop operating voltage from DRAM's typical 1.1V to around 0.8V for roughly 1.5x better energy efficiency; Samsung, which owns its own foundry, is instead using its internal 4nm-class SF4 process paired with 1c (~10nm-class) DRAM core dies, and has demonstrated a 12-hi, 36GB stack with 2,048 I/O pins and 3.3TB/s of bandwidth.
Market-share figures diverge by source and don't always measure the same thing: UBS reportedly projects SK Hynix's 2026 HBM4 share near 48% versus Samsung's 39%, flipping to a narrow Samsung lead in 2027, while a separate Sept. 21 report pegs the current overall HBM gap (including older HBM3E, where SK Hynix's lead is largest) at 17 percentage points. Nvidia's own HBM4 allocation to SK Hynix has been reported anywhere from just over half to roughly two-thirds, depending on the outlet and month — treat any single percentage as a snapshot of a fast-moving negotiation, not a settled fact.
Why it matters for tech + supply chain: every 2027 AI GPU roadmap depends on how many working HBM4 stacks Korea's two memory giants can actually produce — and right now, yield, not raw factory capacity, is the real bottleneck.
Why it matters for tech + supply chain: HBM4's base-die split also means TSMC's logic capacity now indirectly gates memory supply for both Samsung and SK Hynix — a second foundry dependency layered underneath the one everyone already watches at the GPU level.